https://wiki.cern.ch/index.php?action=history&feed=atom&title=Verilog 2026-04-04T08:23:38Z Revision history for this page on the wiki MediaWiki 1.44.0 https://wiki.cern.ch/index.php?title=Verilog&diff=11249&oldid=prev 2026-03-31T16:20:45Z

<p></p> <table style="background-color: #fff; color: #202122;" data-mw="interface"> <col class="diff-marker" /> <col class="diff-content" /> <col class="diff-marker" /> <col class="diff-content" /> <tr class="diff-title" lang="en"> <td colspan="2" style="background-color: #fff; color: #202122; text-align: center;">← Older revision</td> <td colspan="2" style="background-color: #fff; color: #202122; text-align: center;">Revision as of 16:20, 31 March 2026</td> </tr><tr><td colspan="2" class="diff-lineno" id="mw-diff-left-l1">Line 1:</td> <td colspan="2" class="diff-lineno">Line 1:</td></tr> <tr><td class="diff-marker" data-marker="−"></td><td style="color: #202122; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #ffe49c; vertical-align: top; white-space: pre-wrap;"><div>a hardware description language (HDL) used to model electronic systems, <del style="font-weight: bold; text-decoration: none;">standardized </del>as <del style="font-weight: bold; text-decoration: none;">IEEE 1364</del>. [[Category:<del style="font-weight: bold; text-decoration: none;">Abbreviations</del>]] [[Category:<del style="font-weight: bold; text-decoration: none;">FAPlist</del>]]</div></td><td class="diff-marker" data-marker="+"></td><td style="color: #202122; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #a3d3ff; vertical-align: top; white-space: pre-wrap;"><div><ins style="font-weight: bold; text-decoration: none;">'''Verilog''', standardized as '''IEEE 1364''', is </ins>a hardware description language (HDL) used to model electronic systems<ins style="font-weight: bold; text-decoration: none;">. It is most commonly used in the design and verification of digital circuits</ins>, <ins style="font-weight: bold; text-decoration: none;">with the highest level of abstraction being at the register-transfer level. It is also used in the verification of analog circuits and mixed-signal circuits, as well </ins>as <ins style="font-weight: bold; text-decoration: none;">in the design of genetic circuits. </ins></div></td></tr> <tr><td colspan="2" class="diff-side-deleted"></td><td class="diff-marker" data-marker="+"></td><td style="color: #202122; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #a3d3ff; vertical-align: top; white-space: pre-wrap;"><div> </div></td></tr> <tr><td colspan="2" class="diff-side-deleted"></td><td class="diff-marker" data-marker="+"></td><td style="color: #202122; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #a3d3ff; vertical-align: top; white-space: pre-wrap;"><div><ins style="font-weight: bold; text-decoration: none;">For more information, see [[wikipedia:Verilog|Wikipedia]]</ins>. <ins style="font-weight: bold; text-decoration: none;"> </ins></div></td></tr> <tr><td colspan="2" class="diff-side-deleted"></td><td class="diff-marker" data-marker="+"></td><td style="color: #202122; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #a3d3ff; vertical-align: top; white-space: pre-wrap;"><div><ins style="font-weight: bold; text-decoration: none;">[[Category:FAPlist]]</ins></div></td></tr> <tr><td colspan="2" class="diff-side-deleted"></td><td class="diff-marker" data-marker="+"></td><td style="color: #202122; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #a3d3ff; vertical-align: top; white-space: pre-wrap;"><div>[[Category:<ins style="font-weight: bold; text-decoration: none;">Standards</ins>]]</div></td></tr> <tr><td colspan="2" class="diff-side-deleted"></td><td class="diff-marker" data-marker="+"></td><td style="color: #202122; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #a3d3ff; vertical-align: top; white-space: pre-wrap;"><div>[[Category:<ins style="font-weight: bold; text-decoration: none;">Programming languages]]</ins></div></td></tr> <tr><td colspan="2" class="diff-side-deleted"></td><td class="diff-marker" data-marker="+"></td><td style="color: #202122; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #a3d3ff; vertical-align: top; white-space: pre-wrap;"><div><ins style="font-weight: bold; text-decoration: none;">[[Category:Pages linking to Wikipedia</ins>]]</div></td></tr> </table>

Vigen https://wiki.cern.ch/index.php?title=Verilog&diff=8015&oldid=prev 2026-03-23T15:17:01Z

<p>Page created automatically by script</p> <p><b>New page</b></p><div>a hardware description language (HDL) used to model electronic systems, standardized as IEEE 1364. [[Category:Abbreviations]] [[Category:FAPlist]]</div>

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